1. Field of the Invention
The present invention relates to the field of VLSI (Very Large Scale Integration) circuit design, and in particular to a method for VLSI synthesis based on data-driven decomposition (DDD).
2. Background Art
Asynchronous VLSI is heralded for its robustness, low power, and fast average-case performance. Many chip designers, however, are deterred from taking advantage of these qualities by the lack of a straightforward design approach.
In designing asynchronous VLSI systems, the formal synthesis of asynchronous VLSI systems begins with a sequential description of the circuit specification and results in a complex and highly concurrent network of transistors. This is accomplished through the application of a series of transformations that preserve the semantics of the program.
One synthesis method begins by describing circuits using a high-level language, Communicating Hardware Processes (CHP). Successive semantics-preserving program transformations are then applied, each generating a lower-level description of the circuit. The final output is a transistor netlist. This method is correct by construction, and every chip designed using this approach (including a 2M-transistor asynchronous MIPS R3000 microprocessor) has been functional on first silicon. However, until recently, the transformations have all been applied by hand, with heavy dependence upon simulations at every level.